The present invention relates to the field of semiconductor technology. Specifically, embodiments of the invention are directed to transistor device structure and its manufacturing methods.
As semiconductor memory devices become increasingly integrated, the feature size including the channel length of individual devices is gradually reduced. This causes a short channel effect and also increases the junction leakage current. Leakage current was not a significant problem in the past, but it has become a more serious concern now that transistor gates and other chip components measure only a few atoms thick. In a notebook computer, leakage current means short battery life and in a server computer, it means higher power bills. Also, in a nonvolatile memory device, the leakage current leads to degradation of data retention time and other electrical characteristics as the device feature size is reduced.
Further, in small geometry devices, the threshold voltage is often difficult to control, and junction leakage current also becomes more difficult to manage. Therefore, there is a need for an improved transistor device structure.